PMC Sierra Network Card PM8385 User Manual

PM8385  
QuadPHY RT  
Released  
4-Port Gigabit Ethernet and 1/2G Fibre Channel Repeater or Retimer  
Programmable receive input  
termination of 100 ohm or 150 ohm  
differential.  
• Extensive per port backplane  
monitoring for loss of signal, error rates,  
and link level violations.  
• Supports single-ended or differential  
125 MHz reference clock for Gigabit  
Ethernet, or 106.25 MHz reference  
clock for Fibre Channel applications.  
GENERAL  
• Supports four physical interfaces for  
Gigabit Ethernet at 1.25 Gbit/s per  
IEEE 802.3z or Fibre Channel physical  
interfaces at 1.0625 or 2.125 Gbit/s per  
Fibre Channel Physical Interface (FC-  
PI) for repeating or retiming  
Programmable output impedance of  
100 ohm or 150 ohm differential.  
TEST AND CONTROL  
applications.  
• Digital loss of link (DLOL) detect pin  
provides status output for monitoring  
individual or multiple links.  
• DLOL and optional interrupt pin can be  
programmed to indicate:  
HIGH-SPEED INTERFACE  
• Backplane repeating/retiming signal  
integrity features enable standards  
compliance, link extension and robust  
gigabit-serial operation in the hostile  
backplane environment.  
• Provides direct connection to high-  
speed serial backplanes, coax  
stacking cables, or optical / copper  
Small Form Factor Pluggable (SFP)  
modules.  
• Provides non-blocking cross-bar for  
protection switching and data bi-cast,  
multi-cast or broadcast.  
• Fast high-speed serial lock times and  
low device latency.  
• High-speed outputs with selectable  
output amplitude and programmable  
pre-emphasis per port to counteract  
dielectric losses and allow maximum  
reach on printed circuit boards and  
cables.  
• Programmable receive input  
equalization provides robust data  
recovery of highly degraded input  
signals.  
Analog loss of signal.  
Excessive 8B/10B code and disparity  
violations.  
Fibre Channel comma density.  
• Loss of synchronization to detect  
Gigabit Ethernet or Fibre Channel  
framing errors.  
• Internal packet generator and  
comparator features simplify backplane  
and jitter testing via:  
• Minimal board footprint and exceptional  
signal integrity achieved:  
No external components are required  
to interface the high-speed signals  
due to internal AC coupling.  
• Rate detection/auto-selection between  
1G and 2G Fibre Channel.  
Programmable pattern (can be used  
with GE high, low and mixed  
frequency tests).  
BLOCK DIAGRAM  
Rx  
Retimer/  
Monitor  
Rx  
Retimer/  
Monitor  
2
RDIP[1]  
RDIN[1]  
RDIP[2]  
RDIN[2]  
SERDES/  
Reclocker  
SERDES/  
Reclocker  
10  
10  
2
2
2
TDOP[2]  
TDON[2]  
TDOP[1]  
TDON1]  
Tx  
Control  
Tx  
Control  
10  
10  
Cross-bar  
Rx  
Rx  
2
Retimer/  
Monitor  
Retimer/  
Monitor  
RDIP[3]  
RDIN[3]  
RDIP[0]  
RDIN[0]  
SERDES/  
Reclocker  
SERDES/  
Reclocker  
10  
10  
2
2
2
TDOP[3]  
TDON[3]  
TDOP[0]  
TDON[0]  
Tx  
Control  
Tx  
Control  
10  
10  
TCK  
TMS  
TDI  
Pattern  
Generator/  
Comparator  
TDO  
TRSTB  
DLOLB  
Impedance  
Control  
Two Wire  
Interface  
PORT_DLOLB[3:0]  
PORT_2G_RATE[3:0]  
INTRB  
CDRU  
Control Block  
PMC-2030741  
Issue 2  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC.,  
© Copyright PMC-Sierra, Inc. 2003.  
All rights reserved.  
AND FOR ITS CUSTOMERS’ INTERNAL USE  
 

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